Integrated circuits are the most demanding patterning application in every requirement.
These requirements are spelled out in the ITRS Road Map, a document that represents
an industry wide consensus for each "device node". Today, it is expected that the 60 nm
and 45 nm nodes will be patterned by immersion 193 nm lithography using "hyper (> 1.0)
NA" lenses. The patterning technology for the 32 nm node is now the node at which Next
Generation Lithography (NGL) will be applied. The leading choice is still Extreme Ultra
Violet (19 nm) lithography, although there are still several daunting problems to solve
even after well over $1B has been invested. These problems include, source output,
resist line edge roughness, optics life, mask repair and the absence of a pellicle to
protect the masks (Lercel 2005). In 2004, imprint technology was placed on the ITRS
Road Map as one of the alternatives to EUV that the industry needed to watch. Immersion
lithography also has open issues, mostly centered on defect density. A team at IMEC
reported that "hero" data for 90 nm defects of 0.04 per squ cm, was achieved by slowing
the system down to 40 wph (Ronse 2005).
The cost of ownership (COO per wafer) is the fundamental economic driver . The COO
components are; depreciation of capital expense, materials costs, mask cost amortized
over the number of wafers processed for each mask, facility costs, support costs, utilities,
capital utilization excluding all down time when the tool is not running product wafers. The
economics of IC patterning technology is also complicated by the considerations of
different types of integrated circuits.
- Memory has the lowest value per wafer and the greatest number of wafers for a
given mask set and so are sensitive to all cost elements of the operation.
- Microprocessor has the highest value per wafer and moderate runs of wafers per
- ASIC has the smallest runs of wafers, such that the COO can be as high as $300
per wafer and 95% of which is mask amortization.
In addition it is quite common for a mask set to be fabricated, only to find a mistake and
the one or more mask have to be replaced. The net result is mask cost will be the
dominate (or the only significant) cost component for many applications. As the mold
amortization becomes more important, the throughput, footprint and cost of the tool
becomes less important.
The requirements for imprint to be considered for 32 nm node are:
- Resolution - 32 nm half pitch
- Overlay - 12 nm
- Throughput - at least 20 wafers per hour. Amortized over 5 years, 100% utilization
gives a contribution to COO of $3.50 a wafer. Assuming 100 imprints per field,
implies 2 secs per field.
- Random defect density - < 0.01 random defects per squ cm, defect size 50% of
critical dimension or 16 nm.
- Fixed defect density - zero, the mask must be inspected, repaired and perfect
within process life.
- Process life - absolute minimum 25 wafers between cleans. In practice, should be
at least 500 wafers per clean, once every 24 hours or 50,000 imprints per clean.
- System cost around $5M.
- Mask cost - less than $200,000 a mask.
- Mask life - greater than a mask run or 50,000 wafers (contribution to COO $4 a
wafer, mask survives 100 cleans)
ASIC's may accept higher system cost or lower throughput.
For imprint to insert it also needs a particular leverage at a particular mask level. Some
levels that have been considered includes;
- Gate levels - where line edge roughness and control is critical, a early device study
at U Texas has been reported (Smith 2004).
- Contacts levels - imprint contact holes at pitches that are "forbidden" in optical
lithography due to interference effects. Several papers have focused on contacts
including (Nordquist 2004, Resnick 2005-1).
- Dual Damascene - imprint both via and interconnect simultaneously, ideally in a
functional dielectric. The Willson group at University of Texas have made
significant progress to this goal. The most recent report is in (Stewart 2005).
The Princeton team have made T Gate transitors (Tan 2004).
The Lund U team have reported GaInAs/InP circuits based on ballistic Junctions
fabricated by thermal imprnt
The team at HP Labs have been pioneers in molecular devices. A recent report on their
use of imprint can be found at Wu 2004 and Jung 2005.
The Torres group at U Wuppertal have directly patterned sexithiophene (Cedeno 2002).
VTT have shown imprint patterning of polyaniline (Maekela 2001)
Joanneum Research have built an organic TFT by thermal imprint (Palfinger 2004).
Cold welding by imprint has been used to fabricate pentecene TFT devices (Kim 2002).
LED's are discussed in Optical Device Applications
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Electronic Device Applications